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| White Electronic Designs 128Kx24 Asynchronous SRAM, 5V FEATURES 128Kx24 bit CMOS Static Random Access Memory Array Fast Access Times: 12 and 15ns Master Output Enable and Write Control TTL Compatible Inputs and Outputs Fully Static, No Clocks EDI8L24128C DESCRIPTION The EDI8L24128CxxBC is a 5V, three megabit SRAM constructed with three 128Kx8 die mounted on a multilayer laminate substrate. With 12 to 15ns access times, x24 width and a 5V operating voltage, the EDI8L2418C is ideal for creating a single chip memory solution for the Motorola DSP5600x or a two chip solution for the Analog Devices SHARCTM DSP. The single or dual chip memory solutions offer improved system performance by reducing the length of board traces and the number of board connections compared to using multiple monolithic devices. For example, the capacitance load on the data lines for the BGA package is 58% less than a monolithic SOJ solution. The JEDEC Standard 119 lead BGA provides a 44% space savings over using 128Kx8, 300mm wide SOJs and the BGA package has a height of 100mm compared to 148mm for the SOJ packages. Surface Mount Package 119 Lead BGA (JEDEC MO-163), No. 391 Small Footprint, 14mm x 22mm Multiple Ground Pins for Maximum Noise Immunity Single +5V (10%) Supply Operation DSP Memory Solution Motorola DSP5600xTM Analog Devices SHARCTM FIG. 1 PIN CONFIGURATION A B C D E F G H I J K L M N O P Q 1 NC NC DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 NC DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 NC NC 2 A0 A5 NC VCC GND VCC GND VCC GND VCC GND VCC GND VCC NC A9 A13 3 A1 A6 NC GND VCC GND VCC GND VCC GND VCC GND VCC GND NC A10 A14 4 A2 E NC GND GND GND GND GND GND GND GND GND GND GND NC W G 5 A3 A7 NC GND VCC GND VCC GND VCC GND VCC GND VCC GND NC A11 A15 6 A4 A8 NC VCC GND VCC GND VCC GND VCC GND VCC GND VCC NC A12 A16 7 NC NC DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 NC DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 NC NC Pin DESCRIPTION A0-16 E# W# G3 DQ0-23 VCC GND NC Address Inputs Chip Enables Master Write Enable Master Output Enable Common Data Input/Output Power (+5V10%) Ground No Connection A0-A16 G# W# E# 128K x 24 Memory Array DQ0-DQ7 DQ8-DQ15 DQ16-DQ23 White Electronic Designs Corp. reserves the right to change products or specifications without notice. January 2002 Rev. 1 1 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs Absolute Maximum Ratings* Voltage on any pin relative to VSS Operating Temperature TS (Ambient) Commercial Industrial Storage Temperature Power Dissipation Output Current. Junction Temperature, TJ -0.5V to 7.0V 0C to + 70C -40C to +85C -55C to +125C 3 Watts 20 mA 175C Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 4.5 0 2.2 -0.3 EDI8L24128C Recommended Operating Conditions Typ 5.0 0 -- -- Max 5.5 0 VCC+0.3 +0.8 Units V V V V *Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. (f=1.0MHZ, VIN=VCC OR VSS) Parameter Address Lines Data Lines Write & Output Enable Line Chip Enable Lines Symbol CL CD/Q W#, G# E# Max 8 10 8 8 Unit pf pf pf pf Capacitance Truth Table E# H L L L W# X H H L G# X H L X Mode Standby Output Deselect Read Write Output High Z High Z Data Out Data In Power ICC2, ICC3 ICC1 ICC1 ICC1 DC Electrical Characteristics (Vcc = 5V, TA = 25C) Parameter Operating Power Supply Current Standby (TTL) Power Supply Current Full Standby Power CMOS Supply Current Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Symbol ICC1 ICC2 ICC3 ILI ILO VOH VOL Conditions W# = VIL, II/O = 0mA, Min Cycle E# VIH, VIN VIL or VIN VIH, f = 0MHz E# VCC -0.2V VIN VCC -0.2V or VIN 0.2V VIN = 0V to VCC VI/O 0V to VCC IOH = -4.0mA IOL = 8.0mA Min 200 Type 270 45 Max mA mA 10 -- -- -- 2.4 -- 10 -- -- -- A 10 -- 0.4 Units mA A V V AC Test Conditions Fig. 1 Fig. 2 Vcc RL= 50 DOUT Z0= 50 DOUT 255 480 5pf VL=1.5V 30pf Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load VSS to 3.0V 5ns 1.5V Figure 1 Note: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2 White Electronic Designs Corp. reserves the right to change products or specifications without notice. January 2002 Rev. 1 2 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs AC Characteristics Read Cycle Parameter Read Cycle Time Address Access Time Chip Enable Access Time Chip Enable to Output in Low Z1 Chip Disable to Output in High Z1 Output Hold from Address Change Output Enable to Output Valid Output Enable to Output in Low Z1 Output Disable to Output in High Z1 1. This parameter is guaranteed by design but not tested. EDI8L24128C Symbol JEDEC tAVAV tAVQV tELQV tELQX tEHQZ tAVQX tGLQV tGLQX tGHQZ Alt. tRC tAA tACS tCLZ tCHZ tOH tOE tOLZ tOHZ Min 12 12ns Max 12 12 3 6 3 6 0 6 0 3 3 Min 15 15ns Max 15 15 7 7 7 Units ns ns ns ns ns ns ns ns ns AC Characteristics Write Cycle Parameter Write Cycle Time Chip Enable to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Data Hold Time Write to Output in High Z1 Data to Write Time Output Active from End of Write1 Symbol JEDEC tAVAV tELWH tELEH tAVWL tAVEL tAVWH tAVEH tWLWH tELEH tWHAX tEHAX tWHDX tEHDX tWLQZ tDVWH tDVEH tWHQX Alt. tWC tCW tCW tAS tAS tAW tAW tWP tWP tWR tWR tDH tDH tWHZ tDW tDW tWLZ Min 12 9 9 0 0 9 9 10 10 0 0 0 0 0 6 6 3 12ns Max Min 15 9 9 0 0 10 10 11 11 0 0 0 0 0 7 7 3 15ns Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units 6 7 1. This parameter is guaranteed by design but not tested. White Electronic Designs Corp. reserves the right to change products or specifications without notice. January 2002 Rev. 1 3 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs FIG. 2 TIMING WAVEFORM -- READ CYCLE tAVAV A tAVAV EDI8L24128C A tAVQV E# tELQV tEHQZ ADDRESS 1 tAVQV ADDRESS 2 G# tELQX tAVQX tGLQV tGHQZ Q DATA 1 DATA 2 Q tGLQX Read Cycle 1 (W# High; G, E Low) Read Cycle 2 (W# High) FIG. 3 WRITE CYCLE -- W# CONTROLLED tAVAV A E# tELWH tAVWH tWLWH W# D tWHAX tAVWL tDVWH tWHDX DATA VALID tWLQZ Q tWHQX HIGH Z FIG. 4 WRITE CYCLE -- E# CONTROLLED tAVAV A tAVEL E# tAVEH tWLEH tELEH tEHAX W# tDVEH D tEHDX DATA VALID Q HIGH Z White Electronic Designs Corp. reserves the right to change products or specifications without notice. January 2002 Rev. 1 4 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs PACKAGE 391: 119 LEAD BGA JEDEC MO-163 0.866 BSC PIN 1 INDEX EDI8L24128C 0.551 BSC 0.110 MAX. R.060 MAX. (4x) 0.800 BSC 0.050 TYP 0.028 MAX. 0.300 BSC ALL DIMENSIONS ARE IN INCHES ORDERING INFORMATION Commercial (0C to +70C) Part Number EDI8L24128C12BC EDI8L24128C15BC Speed (ns) 12 15 Package No. 391 391 Industrial (-40C to +85C) Part Number EDI8L24128C12BI EDI8L24128C15BI Speed (ns) 12 15 Package No. 391 391 White Electronic Designs Corp. reserves the right to change products or specifications without notice. January 2002 Rev. 1 5 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com |
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